1. Field of the Invention
The present invention relates to a semiconductor integrated circuit comprising a logic circuit block. More specifically, the present invention relates to an improvement of a semiconductor integrated circuit comprising a circuit for switching an active mode/sleep mode of a logic circuit block.
2. Description of Related Art
The operating speed of a logic circuit block of a semiconductor integrated circuit can be made faster by composing the same of low threshold transistors. However, transistor OFF leakage current increases exponentially in line with a threshold value being made lower. In other words, when a logic circuit block is composed of low threshold value transistors, the operating speed becomes faster, but power consumption increases.
Power consumption of a logic circuit block can be reduced by switching an active mode/sleep mode of the logic circuit block. An active mode is a mode for supplying driving voltage to a logic circuit block, and making this logic circuit operate. Conversely, a sleep mode is a mode in which a driving current is not supplied to a logic circuit block. Since it is possible to lower OFF leakage current when a logic circuit block is not in use by setting the logic circuit block to the sleep mode, the power consumption of a semiconductor integrated circuit can be reduced.
However, two disadvantages as follows occur in an integrated circuit which switches active mode/sleep mode.
During a sleep mode, the electric charge of a power supply line inside a logic circuit block is gradually discharged to a ground, and consequently, the electric potential of this power supply line drops to the ground level. Therefore, when switching from a sleep mode to an active mode, the power supply line inside a logic circuit block must be charged from ground potential to power supply potential. For this reason, the logic circuit block requires a certain degree of charging time after being switched to an active mode until it is capable of being used. This charging time constitutes standby time for other circuit blocks inside an integrated circuit, and consequently impedes the high speed processing of the integrated circuit.
A logic circuit block generally comprises a flip-flop and a latch for holding data. However, when a logic circuit block is switched to a sleep mode, since the electric potential of the power supply line drops to ground level, these held data are all lost. Conversely, in a case in which it is not desirable for data being held in a latch or flip-flop to be lost, it is not possible to switch to a sleep mode during non-use, and consequently, power consumption cannot be reduced.
A first object of the present invention is to provide a semiconductor integrated circuit in which standby time, when switching from a sleep mode to an active mode, is short.
A second object of the present invention is to provide a semiconductor integrated circuit in which held data inside a logic circuit block is not lost during a sleep mode.
In order to achieve these objects, a semiconductor integrated circuit related to the present invention comprises a logic circuit having a logic element, which is driven by a driving voltage applied from a dummy power supply line, and a mode-switching circuit, which, during an active mode, supplies to the dummy power supply line a first electric potential for driving a logic element, and during a sleep mode, supplies to the dummy power supply line a second electric potential, which is higher than zero volts, and lower than the first electric potential.
A semiconductor integrated circuit related to the present invention sets a second electric potential to a potential that is higher than zero volts, and lower than a first electric potential. In this manner, the present invention achieves short standby time of the logic circuit when switching from a sleep mode to an active mode, and/or holding data of the logic circuit during a sleep mode.